Staff Silicon Design Engineer (Analog Layout)

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We are committed to transforming lives with AMD technology to enrich our industry, communities, and the world. Our mission is to build products that accelerate next-generation computing experiences, including data centers, AI, PCs, gaming, and embedded systems. We foster a culture of innovation, collaboration, humility, and inclusivity, striving for excellence in execution.

The AMD SerDes Technology Group develops high-performance, multi-protocol wireline transceivers in state-of-the-art CMOS processes. We seek an experienced analog/mixed-signal layout design engineer to join our team in developing SerDes solutions for future AMD CPU and GPU connectivity.

You are passionate about high-speed layout design, creative in solving complex challenges, and a team player with excellent communication skills. You have strong analytical and problem-solving abilities, are eager to learn, and willing to tackle new problems.

1. Design layout of high-speed, high-performance SerDes analog mixed-signal circuits according to project specifications.
2. Perform block-level physical implementation, including floor-planning, power distribution, clock and signal routing, and transistor-level layout.
3. Participate in post-layout circuit performance analysis.
4. Engage in block/IP/chip-level integration activities.
5. Estimate schedules, track progress, and report status.
6. Define layout methodology and flow.
7. Drive layout productivity improvements, such as pcell development and automation.
8. Supervise layout resources, assess and correct layout quality issues, and provide feedback to design teams.

1. 10+ years of layout design experience in advanced nodes (7nm or below).
2. Strong understanding of analog/mixed-signal layout fundamentals, IR, EM, capacitances, RC delay, and self-heating.
3. Experience with high-speed signal routing and shielding.
4. Proficiency in physical verification tools (LVS/DRC/ERC/ANT/ESD).
5. Knowledge of circuit design concepts and IC manufacturing processes.
6. Experience with high-speed SerDes and PLL layout in advanced FinFET processes is a plus.
7. Experience with digital integration flows or SOC flows is beneficial.
8. Familiarity with Cadence SKILL, Perl, Python, Tcl, or similar programming languages.
9. Ability to collaborate effectively with remote and international teams.
10. Excellent teamwork and communication skills.

Bachelors or Masters degree in Electrical Engineering or Computer Engineering.

Benefits are described on AMDs benefits page. AMD is an equal opportunity employer and encourages applications from all qualified candidates, accommodating needs as required by law.

Information :

• Company : AMD
• Position : Staff Silicon Design Engineer (Analog Layout)
• Location : Singapore
• Country : SG