| Position | Senior PCIe IP RTL Engineer — Design & Verification |
| Posted | 25 Jul 2026 |
| Expired | 24 Aug 2026 |
| Company | Bitdeer Group |
| Location | Singapore | SG |
| Job Type | Full Time |
Latest job information from Bitdeer Group for the position of Senior PCIe IP RTL Engineer — Design & Verification. If the Senior PCIe IP RTL Engineer — Design & Verification vacancy in Singapore matches your qualifications, please submit your latest application or CV directly through the updated Jobkos job portal.
Please note that applying for a job may not always be easy, as new candidates must meet certain qualifications and requirements set by the company. We hope the career opportunity at Bitdeer Group for the position of Senior PCIe IP RTL Engineer — Design & Verification below matches your qualifications.
Bitdeer Group in Singapore is looking for an experienced PCIe IP Design Engineer to develop and implement Verilog RTL for PCIe-related IP blocks. This role involves ensuring functional coverage, contributing to both pre-silicon and post-silicon debug activities, and collaborating with various teams to deliver high-quality IP solutions.
The ideal candidate will have at least 5 years of experience in semiconductor R&D, a strong understanding of PCIe architecture, and the ability to work with scripting languages like Perl and Shell.
#J-18808-LjbffrAfter reading and understanding the criteria and minimum qualification requirements explained in the job information Senior PCIe IP RTL Engineer — Design & Verification at the office Singapore above, immediately complete the job application files such as a job application letter, CV, photocopy of diploma, transcript, and other supplements as explained above. Submit via the Next Page link below.
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